Constant Time Sorting on a Processor Array with a Reconfigurable Bus System

Sorting is undoubtedly one of the most fundamental problems in computer science. Many sequential sorting algorithms are available in the literatures [6] and it is well known that this problem requires O(n log n) time in the worst case. To speed-up sorting, many parallel algorithms have been proposed on various parallel machines [2]. Constant time sorting can be achieved on an extremely powerful machine model, CRCW PRAM (concurrent-read concurrent-write parallel random access machine), in which simultaneous access (read or write) to the same memory location is allowed and the write conflict resolution process is to store the sum of all numbers that are written to the same memory location [3]. Although powerful, this machine is too idealistic to be implemented with the current hardware technology. On the other hand, networks of processors such as linear array, perfect shuffle, mesh, tree, and cube seem to be more feasible. However, the sorting times of these networks are bounded below by their diameters, which is by no means a constant. Recently, many processor arrays have been supplemented with buses to decrease their diameters in order to enhance the system performance [1,4,8,15,20]. Buses can give processor arrays greater communication capabilities. They allow broadcasting and long-distance communication to be completed in constant time. A bus system whose configuration can be dynamically changed is called a reconfigurable bus system. Many reconfigurable bus systems such as bus automaton, reconfigurable mesh, and polymorphic-torus network have appeared in the literature [7,10,16,22]. A bus automaton [16,18] can be viewed as a cellular automaton with a locally switchable global communication network. By adjusting the local switches properly, straight, zig-zag, and staircase subbuses can be formed. Efficient algorithms on bus automata for many applications such as pattern recognition [9,17,19], language parsing [14], and string comparison [5], have been proposed. A reconfigurable mesh [lo] consists of a square array of processors which are connected to a grid-shaped reconfigurable broadcast bus system. Within each processor, four locally controllable bus switches are built to adjust the configuration of the bus system. Some graph [ll], image [12], and geometry problems [13] have been efficiently solved on the reconfigurable mesh. Like the reconfigurable mesh, a polymorphic-torus network [7] also consists of a square array of processors, but with a wrap around connection on each row and column. Efficient embeddings of tree, ring, mesh, pyramid, and hypercube can be realized by properly establishing the programmable local switches within each processor [7]. In this paper, we derive a constant time sorting